[The idea of BENEFIT, just born :-)][List of all BENEFIT events] [Moscow94]


Workshop on

Design Methodologies for Microelectronics and Signal Processing

Cracow , Poland,

21-23 October 1993

accompanied by the Seminar on

Control and Modelling of Cancer Cell Population


Special Day on European Co-operation

Gliwice, Poland

20 October 1993



The main aim of the Workshop is to establish links and share experiences between research groups from Eastern and Central Europe with those from the European Community in the area of microelectronics and signal processing, as well as to identify appropriate nodes for "networks of competence" in the area. Besides the regular and short presentations as well as posters this aim is served by ROUND TABLE discussions and an OPEN FORUM session.

A unique in character, whole day SPECIAL SESSION on European Cooperation in Science, Technology and Education based on the Commission of the European Communities Programmes constitutes an integral part of the event. This session is expected to fill an evident gap in information and procedures of cooperation between East, Central and West European countries in science, technology and education based on C.E.C. programmes. It aims at substantially improving know-how in: building up joint proposals for projects, e.g. in the framework of the Community programmes; managing international projects; cooperating in projects, working groups or networks.

The workshop is preceded by an OPEN DAY at the Department of Automatic Control, Electronics and Computer Science of the Silesian Technical University, Gliwice, on October 19th, 1993.

The INTERNATIONAL SEMINAR on Control and Modelling of Cancer Cell Population accompanies the workshop.


Design Methodologies for Microelectronics

1. Design and specification languages
2. Component and system modelling
3. Synthesis
4. Design correctness
5. Education in microelectronics

Design Methodologies for Signal Processing

1. Signal processing in control: design methodologies
2. Parallel and distributed computing
3. Neural networks
4. Signal processing application
5. Education in signal processing


October 20th: Silesian Technical University, Gliwice, Poland, 16 Akademicka St., room A.

October 21-23rd: Holiday Inn Hotel, 11 Armia Krajowa Avenue,
30-150 Krakow, tel.+48 12 375044, fax +48 12 375938


The official language of the workshop is English. It will be used for all printed material, presentations and discussions. No simultaneous translation services will be provided. to the Workshop on Design Methodologies for Microelectronics and Signal Processing

Creating scientific links between eastern and central European Countries and the European Community is a challenging enterprise. The Workshop on Design Methodologies for Microelectronics and Signal Processing is a contribution to this goal.

The somewhat unusual structure of the workshop in two parts strongly reflects this goal. During the first day in Gliwice the aim is to introduce mechanisms and procedures for possible cooperation. The programme includes speakers from the European Community which give an overview on existing programs as well as an introduction to the procedures to apply to these programmes. We also hope to provide an opportunity to establish first contacts among the attendees interested in such links.

The second part of the workshop in Cracow consists of a scientific programme. The response to the call almost overwhelmed the Technical Programme Committee: we received a total of 82 submissions. The most distinguishing characteristic was a very strong participation of Central and Eastern European countries; 50 contributions came from these regions and additional 4 contributions were already product of ongoing cooperation with western european countries. The other 28 submissions came from Western Europe and Israel. The Technical Programme Committee selected 26 contributions as regular presentations. In addition, we made an effort to invite several distinguished speakers in areas of particular interest. Short presentations and posters provide the opportunity to present ideas which the Committee found valuable but which may be presented in a shorter time than a regular presentation. Overall, the technical programme covers many areas in design automation, signal processing and parallel processing, and is a sign of strong and diversified activities of Central and Eastern Europe in these fields.

We would like to take the opportunity to thank all those who contributed to this workshop, in the first place the Commission of the European Communities for their sponsorship, encouragement and support. The organizing committee did an excellent job in Poland (T. Grabowiecki and H. Delewicz) and at GMD (A. Pawlak) where we collected and reviewed the papers, solving all problems that arose in the organization of a new event of this nature. We thank the technical programme committee, the IEEE Polish chapter, IFIP Working Group 10.2, EUROMICRO, and especially all the authors, speakers and session chairs.

We wish all attendees an interesting and highly rewarding workshop!

Wilibald Winkler Raul Camposano
General Chair Technical Chair


Wilibald Winkler
Chancellor of the Silesian Technical University
Gliwice, Poland


Raul Camposano
Sankt Augustin, Germany


Klaus Woelcken
Commission of the European Communities
Brussels, Belgium


Raul Camposano GMD/SET, Germany
Jan Chojcan Silesian Technical University, Gliwice, Poland
Zbigniew Czech Silesian Technical University, Gliwice, Poland
Hubert Emptoz INSA, France
Tadeusz Grabowiecki Silesian Technical University, Gliwice, Poland
Kurt Judmann Technical University of Vienna, Austria
Jean Mermet Universite Joseph Fourier, Grenoble, France
John Molgaard Elektronikzentrale, Denmark
Wolfgang Nebel University of Oldenburg, Germany
Antonio Nunez University of Gran Canaria, Spain
Adam Pawlak GMD/SET, Germany
Paolo Prinetto Politecnico di Torino, Italy
Peter Schwarz Fraunhofer-Institut, Dresden, Germany
Michal Servit Czech Technical University, Prague, Czech Republic
Mario Stevens Technical University Eindhoven, The Netherlands
Ferenc VajdaKFKI Research Institute for Measurement and Computing, Budapest, Hungary
Klaus WoelckenCommission of the European Communities, Brussels, Belgium
Konrad Wojciechowski Silesian Technical University, Gliwice, Poland


Halina Delewicz Silesian Technical University, Gliwice, Poland
Tadeusz Grabowiecki Silesian Technical University, Gliwice, Poland
Adam Pawlak GMD/SET, Germany

Contact Person

Dr Adam Pawlak
Postfach 1316
D-53731 St. Augustin 1

e-mail: pawlak@borneo.gmd.de
tel.:+49 2241 142774
fax: +49 2241 142035

Local organizer

Dr Tadeusz Grabowiecki
Institute of Electronics
Silesian Technical University
ul. Akademicka 16
44-100 Gliwice, Poland

tel.: +48 32 371665, 371495
fax: +48 32 372225_ If the registration has not been paid prior to the workshop, its participants are kindly asked to settle the amount of USD 130 at the desk.


During the OPEN DAY PTH Techmex will make a presentation of computer equipment.

Welcome cocktail in Gliwice

A welcome cocktail, offered by the City Council of Gliwice, will take place on Tuesday, October 20th, at 5.30 p.m., in the City Hall. Dr. Grabowiecki, Chairman of the City Council, will welcome the workshop participants and their companions.

Invitation dinner

An invitation dinner will be served at the Holiday Inn hotel at 9 p.m., October 20th. Every workshop participant and his/her spouse is invited to the dinner.


The Workshop Banquet will be held on Friday, October 22nd at the cafeteria of the Holiday Inn hotel at 8 p.m. Tickets for the banquet (price 300 000 zl - appr. USD 15) can be ordered at the registration desk.

Cracow sightseeing

A guided tour of Cracow includes visit to the medieval Old Town (Town Square, St. Mary's church, Royal Road, Cracow Academy) and castle hill Wawel (the cathedral - kings' of Poland coronation and burial place and the Royal Castle). The tour is included in the registration fee.

Wieliczka salt-mine

A guided tour by bus to the famous medieval salt-mine will be organized after the workshop, on Sunday, October 24th, at 9.30 a.m. Duration of the tour 3.5 to 4 hours, price 240 000 zl (appr. USD 13) per person. Tickets can be ordered at the registration desk.

General information

The Silesian Technical University (the second largest technical university of the country) is recognized as one of the leading universities in Poland. It has been concerned with the education and training of engineers and researchers in various fields of technology.

The Silesian Technical University consists of twelve departments. One of the youngest and yet the largest (regarding both the staff and the number of students) is the Department of Automatic Control, Electronics and Computer Science. The research and educational activities of the Department are focused on electronics (electronic equipment, microelectronics, biomedical electronics), automatic control and robotics, computer science and telecommunications. It maintains close links with industry.

Objectives of the Open Day

The main objective of the Open Day is to enable the guests visiting laboratories and acquainting them with the research carried on at the Department. Moreover the visit is expected to lay the foundations for future cooperation especially within EC projects. Academic staff of the Department is eager to discuss any problem related to research activities and educational curricula with its guests.


As Dean of the Department of Automatic Control, Electronics and Computer Science I would like to invite all participants of the Workshop to visit our Department during the Open Day, October 19, 1993. The University provides free lunch for all visitors this day.

Prof. Jan Chojcan

Technical Programme - October 19th, 1993

Presentation of the Silesian Technical University and the Department of Automatic Control, Electronics and Computer Science (Department of Automatic Control, Electronics and Computer Science bldg, 16, Akademicka St., room A).

11.00 Visit to the laboratories of the Department

14.00 Lunch

15.00 Time for meetings and talks with the staff of the Department

of Automatic Control, Electronics and Computer Science

Special Day on European Co-operation, October 20th, 1993







, Poland,

21-23 October 1993


Round table discussions

Round table discussions on problems relevant or even critical for co-operation will be organized. We plan discussions on: "Main obstacles in building effective EAST-WEST co-operation", "EUROCHIP, how to participate" and "Future of this event". Based on participants proposals further topics will be announced at the workshop.


An OPEN FORUM session will be organized at the workshop to allow for some additional important addresses. The tentative programme of the session is to be found on page 16. The final programme will be announced on site.


The Proceedings has been published by the Silesian Technical University.


October 21 (Thursday)

9.00 Opening address: Raul Camposano, Programme Chairman.

Conference room 1.

9.15 Session 1: High-level synthesis. Conference room 1.

Krzysztof Kuchcinski (Linkoeping University, Sweden)

1.1. Invited lecture: Experiences with high-level synthesis

from VHDL specification
Wolfgang Rosenstiel (University of Tuebingen, Germany)

1.2. High-Level synthesis based on formal methods
W. Grass, M. Mutz, W.-D. Tiedemann (University of Passau, Germany)

1.3. An AI approach to high-level synthesis in the absence of complete information
T. Grabowiecki (Silesian Technical University, Gliwice, Poland)

1.4. Relational semantics for flow graph representations as basis for transformational design of digital systems
C. Huijs, T. Krol (University of Twente, The Netherlands)

Associated poster: 1.

11.15 Coffee break

11.45 Session 2: Education in microelectronics and signal processing. Conference room 1.

Valery M. Mikhov (State Committee on Higher Education of the Russian Federation, Moscow, Russia)

2.1. Invited lecture: Experiences of the EUROCHIP action
Augustin W. Kaesser (GMD/SET, Germany)

2.2. Six years' experience with IC design at the University of Reading
J.R. Miles, S.J. Sangwine (University of Reading, United Kingdom)

2.3. [S] A software toolset for VHDL education and modeling support
W. Sakowski (Silesian Technical University, Gliwice, Poland), W. Wrona (Technical University of Lod-, Poland)

Associated posters: 2 - 7.

12.45 Lunch

[S] denotes short note

14.00 Session 3: Architectures. Conference room 1.

Mario Stevens (Technical University Eindhoven, The Netherlands)

3.1. DCT/IDCT-architectures using residue number systems
D. Birreck, A. Drolshagen, R. Laur (University of Bremen, Germany),St. Walter (Research Centre of DBP Telekom, Darmstadt, Germany)

3.2. New pipelined image processor for morphological operations
S. Fejes, F. Vajda (KFKI Research Institute for Measurement and Computing Techniques, Budapest, Hungary)

3.3. Parallel implementation of a block-matching algorithm for HDTV motion estimation
F.-M. Yang, R. Laur (University of Bremen, Germany) S. Wolter (Research Centre of DBP Telekom, Germany)

3.4. Logical equation solving systolic processor design
Prihozhy (Academy of Sciences of Belarus, Minsk, Belarus), V. Brich (Brest Polytechnic Institute, Belarus),

Associated poster: 8.

14.00 Session 4: Signal processing applications. Conference room 3

Konrad Wojciechowski (Silesian Technical University, Gliwice, Poland)

4.1. Invited lecture: Computer vision and industrial applications
Hubert Emptoz (INSA, Lyon, France)

4.2. Techniques for image compression, demonstration and automatic recognition in a pictorial database
Kivaras (Lithuanian Ministry of Internal Affairs, Vilnius, Lithuania)

4.3. Speech recognition. A full parallel hardware/software development
S. Alexandres, M. Merino, J.M. Meneses (Universidad Politecnica de Madrid, Spain)

4.4.[S] Sensor calibration for video-colorimetry
H. Frey (Technical College Ulm, Germany), H. Palus (Silesian Technical University, Gliwice, Poland)

Associated posters: 8, 9.

16.00 Coffee break

16.30 Session 5: Logic synthesis. Conference room 1.

Michal Servit (Czech Technical University, Prague, Czech Republic)

5.1. General decompositions in logic synthesis
L. Jozwiak (Eindhoven University of Technology, The Netherlands)

5.2. Iterative FSM structuring by partial state assignment
M. Koegst, K. Feske, G. Franke (Fraunhofer-Institut fuer Integrierte Schaltungen, Dresden, Germany)

5.3. A new approach to FPGA-based logic synthesis
T. Luba, H. Selvaraj, A. Krasniewski (Warsaw University of Technology, Poland)

16.30 Session 6: Neural Networks. Conference room 3.

Jan Chojcan (Silesian Technical University, Gliwice, Poland)

6.1. Invited lecture: Use of neural networks in robotics
Dieter Wloka (Universitaet des Saarlandes, Germany)

6.2. Self-organizing maps vs. backpropagation: An experimental study
J. Goeppert, W. Rosenstiel (University of Tuebingen, Germany)

6.3. Synthesizing hardware for neural networks with CADDY/CALLAS
H. Speckmann, P. Thole, W. Rosenstiel (University of Tuebingen, Germany)

6.4.[S] Phonetic typewriter for Lithuanian based on neural networks
Kasparaitis, V. Undzenas (Vilnius University, Lithuania)

October 22 (Friday)

9.00 Session 7: Testing and layout. Conference room 1.

Antonio Nunez (University of Gran Canaria, Spain)

7.1. Invited lecture: Accurate timing verification with correlated component delays
Andrzej Strojwas (Carnegie Mellon University, Pittsburgh, USA)

7.2. The testable measure of entropy type and its application to testable design
D. Speranskiy (Ukrainian Academy of Sciences, Donetsk, Ukraina)

7.3. New approach to weighted self test of the arithmetic unit on a communication processor
S. Bracho, M. Martinez, F. Llacer (University of Cantabria, Santander, Spain)

7.4. Some notes on channel routing
Z.V. Apanovich, A.V. Klekovkin (Institute of Informatics Systems, Novosibirsk, Russia)

11.00 Coffee break

11.15 Session 8: Issues in design automation. Conference room 1.

Tadeusz Grabowiecki (Silesian Technical University, Gliwice, Poland)

8.1. [S] Parallel simulation using an Ada-based event-driven simulator kernel
S.J. Sangwine (University of Reading, United Kingdom)

8.2. [S] The ALFA simulation backplane
M. Zwolicski, T.J. Kazmierski (University of Southampton, United Kingdom), Mrcarica (University of Nis, Yugoslavia)

8.3. [S] Logic simulation and timing analysis for MOS circuits
V.I. Konstantinov (Institute of Informatics System, Novosibirsk, Russia)

8.4. [S] Application of Prolog for verification on the RTL
B. Nowak (Silesian Technical University, Gliwice, Poland)

8.5. [S] Flexible routing method for single-sided PCB
S. Ragaisis (Vilnius University, Lithuania)

11.15 Session 9: Software in parallel processing. Conference room 3.

Zbigniew Czech (Silesian Technical University, Gliwice, Poland)

9.1. Invited lecture: PPPE - a portable, parallel programming environment
A.J.G.Hey (University of Southampton, United Kingdom)

9.2. Invited lecture: Data management for parallel processing
A.G.Chalmers, D.Paddon (University of Bristol, United Kingdom)

9.3. Eliminating forward data dependencies in parallel loops
Z. Szczerbinski (Polish Academy of Sciences, Gliwice, Poland)

Associated posters: 10, 11.

13.00 Lunch

14.15 Session 10: Component modelling in VHDL. Conference room 1.

Adam Pawlak (GMD/SET, Germany)

10.1. Invited lecture: Industrial experimentation of the component modelling standard EIA 567-A
Sylvie Hurat (Thomson-CSF/SCTF, France)

10.2. A technique for a flexible generation of component models
M. Blueml, F. Bouchard, A. Pawlak (GMD/SET, Germany)

10.3. VHDL based software/hardware modeling for simulation and synthesis of DSP algorithms (Case study)
Bakowski, J.-F. Diouris, K. Djigande (IRESTE, Nantes, France)

10.4. [S] VHDL at work
S. Olcoz, J. Goicolea (TGI, Madrid, Spain)

10.5. [S] VHDL models generation with PROLOG in the absence of complete information
A. Pulka (Silesian Technical University, Gliwice, Poland)

Associated posters: 12.

14.15 Session 11: Parallel architectures and algorithms. Conference room 3.

A.J.G. Hey (University of Southampton, United Kingdom)

11.1. Invited lecture: An integrated approach to the development and testing of embedded systems
M. Livesey (University of St Andrews, United Kingdom)

11.2. Parallel searching for a first solution
M. Konopka, Z.J. Czech, B. Bartoszek (Silesian Technical University, Gliwice, Poland)

11.3. Multi-cluster transputer systems with the serial bus-based control of link connections
T. Kalinowski, M. Thor, M. Tudruj (Polish Academy of Sciences, Warsaw, Poland)

11.4. [S] A transputer based implementation of a nearest neighbor classifier
O. Gal, H. Azaria (Ben-Gurion University, Beer Sheva, Israel)

11.5. [S] Parallel signal processing at Aberdeen
A.R. Allen, D. Wang, M.A. Player (University of Aberdeen, United Kingdom)

16.30 Coffee break

17.00 Session 12: Towards formalization of VHDL.

Conference room 1.

Jean Mermet (Universite Joseph Fourier, Grenoble, France)

12.1. Stream semantics for VHDL: An example
L. Sanchez, C.D. Kloos, P.T. Breuer (Universidad Politecnica de Madrid, Spain)

12.2. Synthesis of VHDL subprograms and processes in the CAMAD system
P.Eles, M. Minea (Technical University of Timisoara, Romania),

K. Kuchcinski, Z. Peng (Linkoeping University, Sweden)

12.3. Validation of VHDL systems based on Petri net modeling
E. Encrenaz, J-M. Couvreur, R.K. Bawa (Universite Pierre et Marie Curie, Paris, France)

20.00 Banquet

October 23 (Saturday)

9.00 Session 13: Signal processing. Conference room 1.

Hubert Emptoz (INSA, Lyon, France)

13.1. Invited lecture: Aspects of the theory of morphological operators and filters
H.J.A.M. Heijmans (CWI Amsterdam, The Netherlands)

13.2. Band-limited spectral estimation from partial correlation sequences
T. Chonavel (Franco-Polish School of New Information and Communication Technologies, Poznan, Poland), P. Loubaton (Ecole Nationale Superieure des Telecommunications, Paris, France)

13.3. [S] Analysis of the frequency characteristics of a digital spectral warping network
S. Demidenko (Academy of Sciences of Belarus, Minsk, Belarus), K. Lever (University of South Australia, Levels, Australia)

Associated posters: 13,14.

9.00 Session 14: Vendor presentation. Conference room 3.


Software tools for design automation

Thunborg (Cadence, Munich, Germany)
Vendor Presentation: Tools from CADENCE

CADENCE solutions for framework, design entry, PCB and programmable logic design as well as placement and routing of ICs will be presented.

10.20 Coffee break

10.50 Session 15: Open Forum. Conference room 1.

15.1. Technical policy in Russia today: main directions
V. Boyko (Ministry of Science and Technical Policy of the Russian Federation, Moscow, Russia)

15.2. Electrothermal design of electronic systems
V. A. Koval (Lviv Politechnical Institute, Lviv, Ukraine)

Final programme of the OPEN FORUM will be announced during the workshop.

12.00 Closing session

12.45 Lunch

14.00 Social programme - Cracow sightseeing

October 23 (Saturday)

A tour to Wieliczka salt-mine


1. An integrated design methodology for digital systems
K. Kuchcinski, Z. Peng (Linkoeping University, Sweden)

2. An educational VLSI design project: Implementation of the 32-bit DLX microprocessor
P. Bazargan Sabet, A. Greiner, M-M. Louerat (Universite Pierre etMarie Curie, Paris, France)

3. Program ASIC/DIP implementation in Institute of Electron Technology and Universities
M. Pilch (Institute of Electron Technology, Warsaw, Poland), L. Znamirowski (Silesian Technical University, Gliwice, Poland)

4. SPEC-COM: an instructive comparison of spectral analyze methods
L. Todor (Research Institute for Informatics, Bucharest, Romania)

5. Jump in the digital signal processing with a personal experimentation unit
K. Kardach, J. Majewski (Technical University of Wroclaw, Poland), J. Kopczyk (Computer Systems Design JAS Enterprise, Poland)

6. Training of basic signal processing operations by personal computer for selected streams of mechanical engineering
M. Kosek (Technical University of Liberec, Czech Republic)

7. Experiences with DSP teaching at the University of Reading
J. R. Sangwine (University of Reading, United Kingdom)

8. The multiprocessor system's architecture for a fast image data processing in real time applications
K. Wiatr, J. Kasperek, P. J. Rajda (University of Mining and Metallurgy, Cracow, Poland)

9. CAD tool for HMM based speech recognition ASIC design using VHDL
L. Liras, J. Faura, F. Moreno, J. Meneses (Universidad Politecnica de Madrid, Spain)

10. sccOCC2: A C to occam2 translator and parallelizer
R. Garcia, A. Orgaz, S. Alexandres (Universidad Politecnica de Madrid, Spain)

11. Procedural communication in symmetrical distributed applications
J. Janecek (Czech University of Technology, Prague, Czech Republic)

12. An approach to basic blocks VHDL modelling based on technology
R. Baraniecki, A.T. Rosinski (Institute of Electron Technology, Warsaw, Poland)

13. Nonlinear methods in the regulation of speech tempo
Y. Rushkevych (Lviv Polytechnic Institute, Ukraina)

14. Discrete control uncertain system design based on dynamic compaction method
V. D. Yurkevich (Novosibirsk State Technical University, Russia)






The main objective is to bring together people working on the problems of mathematical modelling of cancer populations and their control, and by the mind fertilization promote new research. By organizing the Seminar as an accompanying event of the Workshop the Programme Committee wants to engage new groups of researchers in this fascinating area. Building a bridge over the gap between biomedical problems and signal processing methodology should be followed by evident progress in understanding of cancer phenomena.


The Proceedings of the Seminar were published in the Journal "Applied Mathematics and Computer Science", Vol. 4 No. 2, ISBN 0867-857X.


Andrzej Swierniak Silesian Technical University, Gliwice, Poland - chairman
Ovide Arino University Pau, France
Marek Kimmel Rice, Houston, USA
Sebastian Anita University Iasi, Romania


October 21 (Thursday)

9.15 Session S1: Problems of Deterministic and Stochastic Modeling of Cancer Cell Population. Conference room 3.

Andrzej Swierniak (Silesian Technical University, Gliwice, Poland)

Seminar opening

1. Invited lecture: Rapid Genome Evolution and Cancer: A Modeling Perspective
Marek Kimmel (Rice University, Houston, USA)

2. A model of cell growth and possibilities of tumor treatment by selective protein depletion
Slobodan Tepic (AO Research Institute Davos, Switzerland), Pawelczyk (Silesian Technical University, Gliwice, Poland)

3. Distributed approach to modeling of cell population
Wojciech Jqdruch (Technical University of Gdansk, Poland)

4. Controllability of nonlinear models arising in modeling ofpopulation dynamics
Jerzy Klamka (Silesian Technical University, Gliwice, Poland)

11.15 Coffee break

11.30 Session S2: Mathematical Analysis and ControlProblems in Tumor Growth Models. Conference room 3.

Giuseppe Starace (Instituto di Medicina Sperimentale, Italy)

1. Invited lecture: Asynchronous exponential growth in cell population
Ovide Arino (Universite de Pau, France)

2. Some control problems for simplest differential models of proliferation cycle
Andrzej Swierniak (Silesian Technical University, Gliwice, Poland)

3. Deterministic and stochastic modeling of tumor growth and optimal chemotherapy
Rimantas Eidukevichius (Vilnius University, Lithuania)

12.45 Lunch

October 22 (Friday)

9.00 Session S3: Optimization in cancer population models and chemotherapy. Conference room 3.


Marek Kimmel (Rice University, Houston, USA).

1. Invited lecture: H infinity methods in population modeling and control
Sebastian Anita (University of Iasi, Romania),

2. Invited lecture: Mathematical methods for cell cycle analysis from flow cytometric DNA-BrdUrd distributions
Alessandro Bertuzzi, Alberto Gandolfi (IASI-CNR, Rome, Italy), Carmela Sinisgali (Universita di Roma, Italy), Giuseppe Starace (Instituto di Medicina Sperimentale, Italy)

3. Evaluation of some optimal chemotherapy protocols by using gradient methods
Zdzislaw Duda (Silesian Technical University, Gliwice, Poland)

4. Irregularity of some problems of optimal scheduling of cancer chemotherapy
Andrzej Swierniak, Andrzej Polanski (Silesian Technical University, Gliwice, Poland)

Gliwice, situated in Upper Silesia (the south-west part of Poland, the most heavily industrialized region of Poland), is one of the oldest cities in the region and in Poland. Gliwice came into being in the second part of the thirteenth century at the crossroads of former trade routes, leading from Moravia and Bohemia to Scandinavia and from Eastern to Western Europe. At the turn of fourteenth and fifteenth centuries the town of Gliwice became notably fortified to reinforce the security of the town.

Politically, Gliwice was under the domination of the Polish Piast dynasty. In the sixteenth century the town experienced the pleasures of economic boom. At the same time the town of Gliwice came under the reign of the Habsburgs until 1740. As a result of the Wars over Upper Silesia between Austria and Prussia in the years 1740-1763, Prussia captured this region.

The outbreak of the Second World War is connected with the history of Gliwice, since it was here, on 31st August 1939, that the broadcasting station was raided by an imaginary troop of Polish soldiers - an "incident" claimed by the Nazis as provocation leading to the outbreak of war.

Today the population of Gliwice is over 200 000. In the post-war period the town of Gliwice has become a great center of science and of modern industry, full of vitality.

Cracow, the former capital of Poland, has been the coronation, residence and burial place of Polish kings. It is situated in the south of Poland on the Vistula River. The first mention of Cracow dates back to 965. The first traces of settlement date back several thousands of years. Gradually, Cracow gained prominence among Polish cities and in the 11th century became the official capital of Poland.

Cracow was endowed with municipal rights in 1257. In the 14th century, Cracow became the city of royal coronations and burials. Under the rule of Kazimierz Wielki (Casimir the Great) a generous patron of arts and science, the city developed and expanded. In 1364, the King founded the Cracow Academy which, after Prague's, is the second oldest University in Central Europe.

In the 15th and 16th centuries, known as the Golden Age, Poland and Cracow flourished. Many artists and scholars settled in Cracow. It was there that the greatest sculptor of Medieval times - Wit Stwosz created his masterpiece: the altar for St. Mary's church. The famous astronomer Nicolaus Copernicus studied at the Academy of Cracow.

Splendid Italian architects worked there creating the Renaissance image of the city. In 1609, King Zygmunt Waza the Third moved his residence to Warsaw. Throughout the 18th century, Cracow was repeatedly besieged, conquered and pillaged by Swedish, Russian, Austrian and Prussian armies. In 1795, when Poland lost its independence, Cracow was incorporated into the Austrian domain.

Since the regaining of Polish independence in 1918, Cracow has remained an important center of culture and science.